Method of manufacturing a semiconductor device

ABSTRACT

A method of manufacturing a semiconductor device, includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent applicationNo. 2003-426943, filed on Dec. 24, 2003, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates in general to a semiconductor device andto a method of manufacturing the same. Specifically, it relates to atechnology that may be effectively used for flip-chip bonding.

For conventional flip-chip bonding using an adhesive, a semiconductordevice having multi-stepped flanks is bonded to a circuit board. Thesemiconductor device and the circuit board are thermally bonded togetherthrough a detection member or an interposed member having amulti-layered structure, and the interposed member is broken orseparated so as to be removed as required after bonding (refer to, forexample, patent document 1).

[Patent document 1] Japanese Unexamined Patent Publication No.2000-216193 (FIG. 1)

SUMMARY OF THE INVENTION

As an example of a semiconductor device making use of flip-chip bonding,there is a multi-chip semiconductor device comprising multiple layers ofsemiconductor chips, in which the semiconductor chip of the lowest layeris flip-chip bonded to a wiring substrate.

The above-described multi-chip semiconductor device will desirably havea narrower pitch of pads (electrodes) from the point of view of sizereduction of the semiconductor device and an increase in the number ofpins. As one means of reducing the size (thickness) of the semiconductordevice, it is proposed to reduce the thickness of the semiconductorchip. That is, the semiconductor chip is made thin by grinding its rearsurface.

In addition, due to a reduction in the pitch of the pads, it is becomingvery difficult to effect under-fill sealing of a flip-chip bondedportion of such a semiconductor device because the permeation of a resintakes time. Therefore, to dial with this problem, an adhesive is appliedto a wiring substrate before semiconductor chips are mounted, and thenthe semiconductor chips are placed on the adhesive and flip-chip bonded,accompanied by the application of pressure and heat.

The inventors of the present invention have conducted studies on thetechnology used for grinding the rear surface of the semiconductor chipof the lowermost layer and pre-coating an adhesive in a multi-chipsemiconductor device and have found the following problem.

That is, when the back surface of the semiconductor chip is pressed toeffect thermal contact bonding of the semiconductor chip, the adhesivepressed by the semiconductor chip rises along the side walls of thesemiconductor chip and reaches the back surface of the semiconductorchip. When grinding marks (unevenness) remain on the back surface of thesemiconductor chip, the adhesive rises onto the back surface by flowingthrough the grinding marks at the edge of the chip, whereby the adhesiveadheres to the back surface of the semiconductor chip forming thelowermost layer. The adhesive is, for example, an epoxy-basednon-conductive (insulating) resin adhesive, mainly a thermosettingresin.

When the resin adhesive adheres to the back surface of the semiconductorchip in this way, the semiconductor chip separates from a sealing resin,or from a die bonding agent (resin adhesive) for the second layer of thesemiconductor chip, because the resin adhesive has poor adhesion to theother resin, and water collects at the site of this separation. Whenassembly is continued in this state, the water expands in response tothe heat applied during a high-temperature treatment (such as solderreflow or the mounting of a substrate) which is carried out later, andthe semiconductor device cracks at the above-mentioned separation site.

It is an object of the present invention to provide a semiconductordevice and a method of manufacturing the same, in which the reliabilityof the device can be improved.

It is another object of the present invention to provide a semiconductordevice which has a reduced thickness and a method of manufacturing thesame.

The above and other objects and features of the present invention willbecome apparent from the following description when taken in conjunctionwith the accompanying drawings.

Typical aspects and features of the invention disclosed in the presentspecification will be briefly described below.

That is, according to a first aspect of the present invention, there isprovided a semiconductor device comprising: a wiring substrate having afront surface and a rear surface; a first semiconductor chip, having amain surface and a back surface, which is flip-chip bonded to the frontsurface of the wiring substrate through projecting electrodes; a secondsemiconductor chip having a main surface and a back surface, which ismounted over the first semiconductor chip by bonding it's the backsurface thereof to the back surface of the first semiconductor chip withan adhesive; a non-conductive resin adhesive interposed between thewiring substrate and the first semiconductor chip; and a sealing body,formed over the front surface of the wiring substrate, for resin sealingthe first and second semiconductor chips, wherein the firstsemiconductor chip is made thin by grinding its back surface, and theback surface is made flat by polishing after grinding.

According to a second aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising the stepsof:

-   -   (a) grinding the rear surface of a semiconductor wafer to reduce        its thickness;    -   (b) after the step (a), flattening the rear surface of the        semiconductor wafer;    -   (c) after the step (b), dividing the semiconductor wafer into a        plurality of semiconductor chips;    -   (d) after the step (c), forming projecting electrodes on the        plurality of semiconductor chips;    -   (e) applying a non-conductive resin adhesive to the front        surface of a wiring substrate;    -   (f) arranging the semiconductor chips over the front surface of        the wiring substrate through the resin adhesive and pressing a        back surfaces of the semiconductor chips to flip-chip bond the        semiconductor chips to the wiring substrate through the        projecting electrodes; and    -   (g) sealing the semiconductor chips with a resin.

According to a third aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising the stepsof:

-   -   (a) grinding the rear surface of a semiconductor wafer to reduce        its thickness;    -   (b) after the step (a), planishing the rear surface of the        semiconductor wafer;    -   (c) after the step (b), dividing the semiconductor wafer into a        plurality of semiconductor chips;    -   (d) after the step (c), forming projecting electrodes on the        plurality of semiconductor chips;    -   (e) applying a non-conductive resin adhesive to the front        surface of a wiring substrate;    -   (f) arranging the semiconductor chips over the front surface of        the wiring substrate through the resin adhesive;    -   (g) after the step (f), pressing the planished back surfaces of        the semiconductor chips to flip-chip bond the semiconductor        chips to the wiring substrate through the projecting electrodes;        and    -   (h) sealing the semiconductor chips with a resin.

According to a fourth aspect of the invention, there is provided amethod of manufacturing a semiconductor device, comprising the steps of:

-   -   (a) preparing a plurality of semiconductor chips, each having a        main surface and a back surface, the back surface being ground        to be made thin, and being flattened after grinding;    -   (b) forming projecting electrodes on the electrodes of the        plurality of semiconductor chips;    -   (c) applying a non-conductive resin adhesive to the front        surface of a wiring substrate;    -   (d) arranging the semiconductor chips over the front surface of        the wiring substrate through the resin adhesive;    -   (e) pressing the flattened back surfaces of the semiconductor        chips to flip-chip bond the semiconductor chips to the wiring        substrate through the projecting electrodes; and    -   (f) sealing the semiconductor chips with a resin.

The effect obtained from typical features of the invention disclosed inthe present patent application will be briefly described as follows.

The rear surface of the semiconductor wafer is ground to reduce thethickness, and, further, irregularities on the rear surface of thesemiconductor wafer are removed by flattening the rear surface. Thereby,it is possible to prevent the resin adhesive from rising onto the backsurface of a chip during flip-chip bonding, and to prevent separationbetween the back surface of the chip and the sealing resin and betweenthe back surface of the chip and the die bonding material of a secondsemiconductor chip. As a result, the above-described separation andcracking previously caused by a high-temperature treatment used duringassembly or mounting of a semiconductor device can be prevented.Accordingly, the reliability of the semiconductor device can beimproved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a semiconductor device according to anembodiment of the present invention;

FIG. 2 is an assembly flow diagram showing a method of manufacturing thesemiconductor device shown in FIG. 1;

FIG. 3 is a flow diagram showing in sectional view the assembly statescorresponding to steps S1 to S5 of the assembly flow shown in FIG. 2;

FIG. 4 is a flow diagram showing in sectional view the assembly statescorresponding to steps S6 to S9 of the assembly flow shown in FIG. 2;

FIG. 5 is a flow diagram showing in sectional view the assembly statescorresponding to steps S10 and S11 of the assembly flow shown in FIG. 2;

FIG. 6 is a flow diagram showing in sectional view the assembly statescorresponding to steps S12 and S13 of the assembly flow shown in FIG. 2;

FIG. 7 is a flow diagram showing in perspective view the states of awafer corresponding to steps S1 to S4 of the assembly flow shown in FIG.2;

FIG. 8 is a sectional view showing an NCP application method in the NCPapplication step of the assembly flow shown in FIG. 2;

FIG. 9 is a sectional view showing a temporary mounting method in the FCmounting step of the assembly flow shown in FIG. 2;

FIG. 10 is a sectional view showing a main contact bonding method in theFC mounting step of the assembly flow shown in FIG. 2;

FIG. 11 is a partially enlarged sectional view showing the structure ofportion A shown in FIG. 10;

FIG. 12 is a partially enlarged sectional view showing a contact bondingmethod according to a modification of the embodiment of the presentinvention;

FIG. 13 is a partial sectional view showing the mounting of thesemiconductor device shown in FIG. 1 to a packaging board;

FIG. 14 is a partially enlarged sectional view showing the contactbonding method of a Comparative Example, in contrast to the main contactbonding method shown in FIG. 10; and

FIG. 15 is a plan view showing the adhesion of a resin adhesive to aback surface of a chip by the contact bonding method of the ComparativeExample shown in FIG. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A description of the same or similar parts is not repeated in thefollowing description of the embodiments, unless it is especiallynecessary.

Further, in the following description of the embodiments, if necessaryfor convenience's sake, the present invention may be described as aplurality of sections or embodiments, but they are not to be consideredirrelevant to each other, to be considered as one is a modification,detailed description or complementary explanation of part or all of theother, unless otherwise stated.

In the following description of the embodiments, when numerical figures(including the number, numerical value, amount and range) for elementsare referred to, it is to be understood that the present invention isnot limited to these specific numerical figures and may be larger thanand smaller than the specified numerical figures, unless they areclearly specified and obviously limited to the specific figurestheoretically.

Preferred embodiments of the present invention will be described indetail with reference to the accompanying drawings. In all the figures,members having the same function are given the same reference symbols,and a repeated description thereof will be omitted.

Embodiments

The semiconductor device of the embodiment shown in FIG. 1 has astructure in which a semiconductor chip is flip-chip bonded to a wiringsubstrate. In this embodiment, an SIP (System In Package) 16 having foursemiconductor chips and which is sealed with a resin will be describedas an example of the above-mentioned semiconductor device.

The SIP 16 comprises a first semiconductor chip 1 for control, a secondsemiconductor chip 2, a third semiconductor chip 3 and a fourthsemiconductor chip 4, each having a memory circuit. The firstsemiconductor chip 1 of these semiconductor chips is flip-chip bonded toa packaging board 5, which serves as a wiring substrate, throughprojecting electrodes, and the second semiconductor chip 2 is formedover the first semiconductor chip 1. The third semiconductor chip 3 ismounted over the packaging board 5, and the fourth semiconductor chip 4is mounted over the third semiconductor chip 3 in such a manner thattheir main surfaces 3 a and 4 a face up.

Only the first semiconductor chip 1 is flip-chip bonded to the packagingboard 5. The second semiconductor chip 2, the third semiconductor chip 3and the fourth semiconductor chip 4 are wired to the packaging board 5.

As for the detailed structure of the SIP 16 shown in FIG. 1, the SIP 16comprises the packaging board 5, which serves as a wiring substratehaving a front surface 5 a and a rear surface 5 b; the firstsemiconductor chip 1 which has a main surface 1 a and a back surface 1 band is flip-chip bonded to the front surface 5 a of the packaging board5 through projecting electrodes; the second semiconductor chip 2, whichhas a main surface 2 a and a back surface 2 b and is formed over thefirst semiconductor chip 1 in such a manner that its back surface 2 b isconnected to the back surface 1 b of the first semiconductor chip 1 by adie bonding agent (adhesive) 12; the third semiconductor chip 3, whichis formed over the front surface 5 a of the packaging board 5 in such amanner that its main surface 3 a faces up; the fourth semiconductor chip4, which is formed over the main surface 3 a of the third semiconductorchip 3 in such a manner that its main surface 4 a faces up; a NCP(Non-Conductive Paste) 7, which is a non-conductive resin adhesiveinterposed between the front surface 5 a of the packaging board 5 andthe first semiconductor chip 1; a plurality of wires 6 for electricallyconnecting the second, third and fourth semiconductor chips to thepackaging board 5; a sealing body 10 for sealing the four semiconductorchips and the plurality of wires 6 with a resin; and a plurality ofsolder balls 11, which serve as external terminals formed on the rearsurface 5 b of the packaging board 5.

Further, the back surface 1 b of the first semiconductor chip 1 of theSIP 16 is made thin by grinding and flat by polishing after grinding.That is, the back surface 1 b is planished.

The back surface 1 b of the first semiconductor chip 1 is ground toreduce the thickness of the semiconductor chip 1 to about 140 μm. Theother three semiconductor chips may be made thin likewise, as required.

The first semiconductor chip 1 is flip-chip bonded to the packagingboard 5 by gold bumps (projecting electrodes) 1 d, which are soldered tothe packaging board 5 for flip-chip bonding. The NCP 7, which is a resinadhesive, is interposed between the packaging board 5 and the firstsemiconductor chip 1 to harden and protect the flip-chip bondedportions. The NCP 7 is, for example, an epoxy-based non-conductive(insulating) thermosetting resin adhesive.

The second semiconductor chip 2, the third semiconductor chip 3 and thefourth semiconductor chip 4 are fixed by the die bonding agent 12. Thatis, as the second semiconductor chip 2 is formed over the firstsemiconductor chip 1, the back surface 1 b of the first semiconductorchip 1 is bonded to the back surface 2 b of the second semiconductorchip 2 by the die bonding agent 12. Further, as the back surface 3b ofthe third semiconductor chip 3 is bonded to the packaging board 5 by thedie bonding agent 12, and the fourth semiconductor chip 4 is formed overthe main surface 3 a of the third semiconductor chip 3, the main surface3 a of the third semiconductor chip 3 and the back surface 4 b of thefourth semiconductor chip 3 are bonded together by the die bonding agent12.

Due to the above-described arrangement, the main surface 2 a of thesecond semiconductor chip 2, the main surface 3 a of the thirdsemiconductor chip 3 and the main surface 4 a of the fourthsemiconductor chip 4 face up and can be wired.

The die bonding agent 12 is, for example, an epoxy-based non-conductive(insulating) thermosetting resin adhesive as well. The sealing resin forforming the sealing body 10 is, for example, an epoxy-based insulatingthermosetting resin. The wire 6 is a conductive wire, for example, agold wire.

The plurality of external terminals on the rear surface 5 b of thepackaging board 5 are solder balls 11, and they are arranged in alattice on the rear surface 5 b of the packaging board 5. That is, theSIP 16 of this embodiment is also a BGA (Ball Grid Array) typesemiconductor device.

As shown in FIG. 5, a plurality of leads (electrodes) 5 c and aplurality of wire connection leads 5 f are formed on the front surface 5a of the packaging board 5, and the areas of the front surface 5 a,excluding these exposed portions are covered with a solder resist film 5i, which is an insulating film. Bump lands 5 h, on which the solderbumps 11 are formed, are provided on the rear surface 5 b. The leads 5 cand the wire connection leads 5 f on the front surface 5 a areelectrically connected to the bump lands 5 h on the rear surface 5 b byinternal wires 5 e and through hole wires 5 g.

Thereby, the electrodes of the semiconductor chips are electricallyconnected to the solder balls 11, which constitute external terminalsformed on the rear surface 5 b of the packaging board 5. The leads 5 c,the wire connection leads 5 f and the through hole wires 5 g are made ofcopper alloy.

In the SIP 16 of this embodiment, the first semiconductor chip 1, whichis flip-chip bonded to the packaging board 5, is made thin by grinding(also called “back-grinding”) the back surface 1 b before the wafer isdivided into chips and flattened by polishing or wet-etching aftergrinding. Therefore, the back surface 1 b has a high flatness.Consequently, since the irregularities 9 c in the Comparative Exampleshown in FIG. 14 are not formed on the back surface 1 b of the firstsemiconductor chip 1, as shown in FIG. 10, it is possible to prevent theNCP 7 from rising up and flowing onto the back surface 1 b, whenpressure is applied thereto by a pressure block 13 for flip-chipbonding, and, therefore, the adhesion of the NCP 7 to the back surface18 a of the chip 18, as seen in the Comparative Example shown FIG. 15,is prevented.

As a result, separation between the back surface 1 b of the firstsemiconductor chip 1 and the sealing body 10, and between the backsurface 1 b of the first semiconductor chip 1 and the die bonding agent12 of the semiconductor chip 2, can be prevented, and also theconsequent separation or cracking caused by a high-temperature treatmentfor forming the solder balls 11 or for mounting the substrate can beprevented. Thereby, the reliability of a semiconductor device, such asthe SIP 16, can be improved.

Since the flip-chip bonded first semiconductor chip 1 is flattened bypolishing or wet-etching after grinding is applied to its back surface,and more of the irregularities 9 c shown in FIG. 14 remain on the backsurface 1 b, the bending strength of the first semiconductor chip 1 canbe improved.

Therefore, the breakage of the chip, which occurs when it is pressed bythe pressure block 13 for flip-chip bonding, can be prevented, and thesecond semiconductor chip 2 can be formed over the first semiconductorchip 1, which has been reduced in thickness. That is, since a thin chipcan be used for flip-chip bonding, a multi-chip semiconductor device,such as the SIP 16, can be is reduced in thickness and size.

The above-described back-grinding step is characterized in that thegrinding speed is faster, but the surface roughness of the back surfaceafter the end of the step is higher than that produced by theabove-referenced polishing step or wet-etching step. It is possible toemploy only back-grinding to reduce the thickness of a wafer. In thiscase, however, as described above, the rising of the adhesive caused bypressure applied thereto and a flowing of the adhesive onto the backsurface of the chip due to the high roughness of the back surface of thechip becomes a problem to be solved. It is also possible to employ onlypolishing or wet-etching for obtaining a very flat surface reduce thethickness of the wafer. In this case, since the polishing or wet-etchingstep has a lower thickness reducing speed than the back-grinding step,the time required for the step becomes long the and productivity isreduced. In order to improve the flatness of the back surface of thechip, while maintaining a good productivity, a step of reducing thethickness at a high speed, for example, by back-grinding, should befirst carried out to reduce the thickness of the wafer to a certaindegree, followed by the step of increasing the flatness of the rearsurface, for example, by polishing or wet-etching, to further reduce thethickness of the wafer. In this case, to maintain the desiredproductivity, the step of reducing the thickness of the wafer at a highspeed is preferably employed so as to reduce the thickness by more thanhalf to achieve a thickness close to the final thickness of the wafer.

A method of manufacturing a semiconductor device according to thisembodiment will be described with reference to the assembly processingflow shown in FIG. 2.

The processing of the wafer is first carried out in step S1 shown inFIG. 2. That is, as shown in step S1 in FIG. 3 and FIG. 7, asemiconductor wafer 9, having a pattern formed on the front surface 9 a,is prepared.

Thereafter, BG (back grinding), as shown in step S2 of FIG. 2, isperformed, that is, the rear surface 9 a of the semiconductor wafer 9 isground to reduce the thickness of the semiconductor wafer 9. As shown instep S2 of FIG. 3, irregularities 9 c are formed on the rear surface 9 bof the semiconductor wafer 9 by such grinding. The irregularities 9 care as large as about 0.05 to 0.1 μm, but they are not limited to thisrange. As shown in step S2 of FIG. 7, grinding marks 9 d are formedradially on the rear surface 9 b of the semiconductor wafer 9.

Thereafter, dry polishing, as shown in step S3 of FIG. 2 is carried outto flatten the rear surface 9 b of the semiconductor wafer 9. In thisstep, the rear surface 9 b of the semiconductor wafer 9 is planished bysuch dry polishing, as shown in step S3 of FIG. 7. Dry polishing isemployed to grind (polish) the surface with a polishing cloth formed bycompressing fibers impregnated with silica to about 2 μm. Theirregularities 9 c on the rear surface 9 b of the semiconductor wafer 9are as large as about 0.0015 μm after dry polishing.

Thereby, the semiconductor wafer 9 is made thin, as shown in step S3 ofFIG. 3. The thickness of the semiconductor wafer 9 which has beenreduced in thickness is, for example, 140 μm and is set to this value asrequired (for example, the wafer can be made as thin as about 90 μm byback-grinding and dry polishing).

Not only dry polishing, but also wet etching, may be used for theflattening of the rear surface 9 b of the semiconductor wafer 9 afterback-grinding. In this case, the wet etching is in the form of spinetching, which is carried out by supplying fluoronitric acid whileturning the semiconductor wafer 9 with a spinner, and it can make theirregularities 9 c smaller than dry polishing.

Thereafter, chip dicing, as shown in step S4 of FIG. 2, is carried out.That is, the semiconductor wafer 9, which has been reduced in thickness,is cut so as to be divided into a plurality of semiconductor chips(first semiconductor chips 1), as shown in step S4 of FIG. 3. At thispoint, as shown in step S4 of FIG. 7, the semiconductor wafer 9 is dicedalong dicing lines 9 e.

Since the irregularities 9 c as seen in the Comparative Example shown inFIG. 14 are not formed on the back surface 1 b of the firstsemiconductor chip 1, the bending strength of the first semiconductorchip 1 can be improved.

Thereafter, stud bumps are formed, as shown in step S5 of FIG. 2. Thatis, projecting electrodes are formed on a plurality of electrodes of thesemiconductor chips. For example, a gold bump 1d is formed as theprojecting electrode on the pads 1c, which are electrodes of the firstsemiconductor chip 1. Wire bonding technology is used to form the goldbumps 1 d (the formed bumps are called “stud bumps”) on the pads 1 d ofthe first semiconductor chip 1. The areas around the sites where the pad1 c is formed of the main surface 1 a of the first semiconductor chip 1are covered with a surface protective film 1 e.

The processing of the wiring substrate in steps S6 and seq. of FIG. 2will be described hereinbelow.

A packaging board 5, which constitutes the wiring substrate shown instep S6 of FIG. 4, is prepared. A plurality of leads 5 c are formed onthe front surface 5 a of the packaging board 5, and a solder resist film5 i, which is an insulating film, is formed around the leads 5 c.

Assembly of parts in step S6 and seq. of FIG. 2 may be carried out byusing a multi-cavity substrate having a plurality of wiring substrates.In this embodiment, the assembly of one SIP 16 using the packaging board5 will be described.

Thereafter, solder pre-coating in step S7 of FIG. 2 is carried out. Thatis, as shown in step S7 of FIG. 4, a solder pre-coat 5 d is formed onthe leads 5 c to be flip-chip bonded on the front surface 5 a of thepackaging board 5. This solder pre-coat 5 d is provided to enhance thesolder bonding strength between the gold bumps 1 d, which are projectingelectrodes, and the leads 5 c for flip-chip bonding.

Thereafter, NCP coating, as shown in step S8 of FIG. 2, is carried out.That is, as shown in step S8 of FIG. 4, an NCP 7, which is anon-conductive resin adhesive, is applied to the front surface 5 a ofthe packaging board 5. The NCP 7 is, for example, a thermosetting resin.

In the method of manufacturing a semiconductor device according to thisembodiment, before flip-chip bonding, the NCP 7 is arranged at portionsof the packaging board 5 to be flip-chip bonded. This is because thegold bumps 1 d become small when the pad pitch is narrowed to increasethe number of pins, whereby the space between the semiconductor chip andthe packaging board 5 becomes small (for example, 5 to 10 μm), therebymaking it extremely difficult to inject a resin by under-fill sealingafter the flip-chip bonding. Therefore, the NCP 7 is arranged on thepackaging board 5. Even if the resin can be injected, since theabove-mentioned space is narrow, it takes very long for the resin toflow between the chip and the substrate. Therefore, the NCP 7 isarranged on the packaging board 5 in advance.

Thereby, even when the pad pitch is reduced in size, the NCP 7, which isa non-conductive resin adhesive, can be inserted between thesemiconductor chip and the packaging board 5.

In this embodiment, as shown in FIG. 8, NCP 7 in the form of a paste isdropped on the front surface 5 a of the packaging board 5 from a nozzle8 so as to be applied to the front surface 5 a. The non-conductive resinadhesive is not limited to a paste resin adhesive, but a film-like resinadhesive (for example, NCF (Non-Conductive Film)) may be used.

Preferably, the NCP 7 is applied as much as possible to cover the areasaround the sides of the semiconductor chip to protect it.

Thereafter, FC (flip chip) mounting, that is, flip-chip bonding, asshown in step S9 of FIG. 2 and FIG. 4, is carried out. First, as shownin FIG. 9, the first semiconductor chip 1, which has been adsorbed andcarried by an adsorption block 13 b, is temporarily mounted over thefront surface 5 a of the packaging board 5 the NCP 7 layer.

Subsequently, as shown in FIG. 10, the planished back surface 1 b of thefirst semiconductor chip 1 is pressed by the pressure block 13 andheated so that the first semiconductor chip 1 is flip-chip bonded to thepackaging board 5 through the gold bumps 1 d. For example, thetemperature of the pressure block 13 is set to 300° C. and the firstsemiconductor chip 1 is pressed by a load of 500 g. Heat applied fromthe pressure block 13 is transmitted to the first semiconductor chip 1to melt the NCP 7 and the solder pre-coat 5 d. That is, this isflip-chip bonding by thermal contact.

Thereby, the solder pre-coat 5 d is heated to a molten state to bond thegold bumps 1 d to the leads 5 c by way of the solder 17, as shown instep S9 of FIG. 4.

In this embodiment, when the back surface 1 b of the first semiconductorchip 1 is to be pressed by the pressure block 13, a sheet member 14 isinterposed between the first semiconductor chip 1 and the pressure block13, as shown in FIG. 11, to press the back surface 1 b of the firstsemiconductor chip 1 by means of the pressure block 13, through thesheet member 14. The sheet member 14 has a thickness of about 50 μm, forexample, and it is made of a fluororesin, for example. Since thefluororesin has high heat resistance and high releasability from aresin, a sheet member 14 made of a fluororesin is preferably used.

In this embodiment, the back surface 1 b of the first semiconductor chip1 to be flip-chip bonded is ground and then polished or wet etched so asto be flattened. Therefore, since the back surface 1 b is very flat andhas no large irregularities 9 c of the type shown in the ComparativeExample of FIG. 14, it is possible to prevent the NCP 7 from rising upand flowing onto the back surface 1 b when the back surface 1 b ispressed by the pressure block 13, as shown in FIG. 11.

That is, since the back surface 1 b of the first semiconductor chip 1 isa planished flat surface, when the first semiconductor chip 1 is pressedby the pressure block 13, it is possible to prevent the NCP 7 that isrising along the side surfaces of the chip from flowing onto andadhering to the back surface 1 b of the first semiconductor chip 1 in aspace between the back surface 1 b of the first semiconductor chip 1 andthe sheet member 14, unlike the case where the NCP 7 flows onto andadheres to the back surface 18 a of the chip 18, as seen shown in theComparative Example of FIG. 15.

Further, since the pressing surface 13 a of the pressure block 13 iscovered with the sheet member 14, when the NCP 7 rises up, it ispossible to prevent the NCP 7 from flowing onto and adhering to thepressure block 13 and the pressure block 13 from being stained by theNCP 7.

The first semiconductor chip 1 is made as thin as about 140 μm, and sothe pressure load of the pressure block 13 cannot be made larger thanrequired in consideration of the bending strength of the semiconductorchip 1. Therefore, as a means of preventing the NPC 7 from flowing ontoand adhering to the back surface 1 b of the first semiconductor chip 1with more certainty, a sheet member 14 that is formed as a thick sheet,as shown in the modification of FIG. 12, may be used.

For example, a sheet member 14 as thick as about 100 μm is used, and theback surface 1 b of the first semiconductor chip 1 is pressed to such anextent that it bites the sheet member 14, whereby the sheet member 14and the back surface 1 b of the first semiconductor chip 1 can adhereclosely to each other. Therefore, it is possible to surely prevent theNCP 7 from flowing onto and adhering to the back surface 1 b of thefirst semiconductor chip 1.

When the first semiconductor chip 1 is pressed using the pressure block13, the sheet member 14 does not always need to be interposed betweenthem. That is, when the adhesion of the NCP 7 to the back surface 1 b ofthe first semiconductor chip 1 can be prevented without interposing thesheet member 14, due to close contact between the pressing surface 13 aof the pressure block 13 and the back surface 1 b of the firstsemiconductor chip 1 resulting from the back surface 1 b of the firstsemiconductor chip 1 being a planished flat surface, the back surface 1b of the first semiconductor chip 1 may be pressed by the pressure block13 without interposing the sheet member 14 therebetween.

The flip-chip bonding of the first semiconductor chip 1 is thuscompleted as shown in step S9 of FIG. 4.

The die bonding of the third semiconductor chip 3 in the SIP 16 is thencarried out. As shown in FIG. 1, the third semiconductor chip 3 isbonded to the front surface 5 a of the packaging board 5 by the diebonding agent 12 while the semiconductor chip is arranged in such amanner that the main surface 3 a faces up. The die bonding agent 12 is,for example, a thermosetting resin adhesive.

Then, a second chip bonding is carried out, as shown in step S10 of FIG.2. As shown in FIG. 1 and step S10 of FIG. 5, the second semiconductorchip 2 is fixed on the first semiconductor chip 1 and the fourthsemiconductor chip 4 is fixed on the third semiconductor chip 3 by thedie bonding agent 12, which is an adhesive.

That is, the semiconductor chip 2 is mounted over the back surface 1 bof the first semiconductor chip 1 through the die bonding agent 12 whilethe semiconductor chip 2 is arranged in such a manner that its mainsurface 2 a faces up, and the back surface 1 b of the firstsemiconductor chip 1 and the back surface 2 b of the secondsemiconductor chip 2 are bonded together by the die bonding agent 12.

Further, the fourth semiconductor chip 4 is mounted over the mainsurface 3 a of the third semiconductor chip 3 through the die bondingagent 12 while the semiconductor chip 3 is arranged in such a mannerthat its main surface 4 a faces up, and the main surface 3 a of thethird semiconductor chip 3 and the back surface 4 b of the fourthsemiconductor chip 4 are bonded together by the die bonding agent 12.

The above-mentioned die bonding agents 12 are, for example, athermosetting resin adhesive.

Thereafter, wire bonding (W/B), as shown in step S11 of FIG. 2, iscarried out. As shown in FIG. 1 and step S11 of FIG. 5, the secondsemiconductor chip 2, the third semiconductor chip 3 and the fourthsemiconductor chip 4 are electrically connected to the wire connectionleads 5 f of the packaging board 5 by wires 6, such as gold wires.

Molding as shown in step S12 of FIG. 2 is then carried out. As shown inFIG. 1 and step S12 of FIG. 6, the first semiconductor chip 1, thesecond semiconductor chip 2, the third semiconductor chip 3, the fourthsemiconductor chip 4 and a plurality of wires 6 are sealed with a resinto form a sealing body 10. The sealing resin used for resin sealing is,for example, an epoxy-based thermosetting resin.

Thereafter, solder ball fixing, as shown in step S13 of FIG. 2, iscarried out. As shown in FIG. 1 and step S13 of FIG. 6, a plurality ofsolder balls 11, which serve as external terminals, are formed on thebump lands 5 h of the rear surface 5 b of the packaging board 5. Thesolder balls 11 are heated to a molten state by a high-temperaturetreatment with a reflow so as to be fixed on the bump lands 5 h.

Since adhesion of the NCP 7 to the back surface 1 b of the firstsemiconductor chip 1 can be prevented in this embodiment, separationbetween the back surface 1 b of the first semiconductor chip 1 and thesealing body 10 and separation between the back surface 1 b of the firstsemiconductor chip 1 and the die bonding agent 12 of the secondsemiconductor chip 2 can be prevented.

This makes it possible to prevent the above-described separation andcracking that are caused by a high-temperature treatment with a reflowfor fixing the solder balls 11, therefore making it possible to improvethe reliability of the SIP 16 (semiconductor device).

When assembly is carried out by using a multi-cavity substrate, thesubstrate is cut into individual SIP's 16, as shown in step S14 of FIG.2.

Since bonding between the solder balls 11 and the terminals 15 a of thepackaging board 15 is carried out by a high-temperature treatment with areflow for mounting the SIP 16 over the packaging board 15, as shown inFIG. 13, separation between the back surface 1 b of the firstsemiconductor chip 1 and the sealing body 10 and between the backsurface 1 b of the first semiconductor chip 1 and the die bonding agent12 of the second semiconductor chip 2 and cracking can be prevented,thereby making it possible to improve the reliability of the SIP 16.

A method of manufacturing a semiconductor device according to thisembodiment has been described above for a case in which the step ofreducing the thickness of the semiconductor wafer 9 by grinding the rearsurface 9 b is first carried out. Alternatively, in another example, aplurality of semiconductor chips which are made thin by grinding theback surfaces 1 b and made flat by flattening the back surfaces 1 bafter grinding are prepared, stud bumps are formed on thesesemiconductor chips, as shown in step S5 of FIG. 2, and thesemiconductor chips having gold bumps 1 d are flip-chip bonded toassemble the semiconductor devices. That is, semiconductor chips whichhave been subjected to the steps S1 to S4 in FIG. 2 are fed, and stepsS5 to S14 of FIG. 2 are carried out on these semiconductor chips toassemble the semiconductor devices.

While preferred embodiments of the invention which was made by thepresent inventors have been described above, it is needless to say thatthe present invention is not limited to the above-described embodimentsand may be modified without departing from the spirit and scope of theinvention.

For example, in the above-described embodiments, the gold bumps 1 d arethermally contact bonded to the leads 5 c of the packaging board 5 bysolder bonding. However, the flip-chip bonding may be carried out byplating the surface of the leads 5 c of the packaging board 5 with goldto contact-bond the gold bumps 1 d to the gold plating of the leads 5 c.

While the SIP 16 has been described as an example of the semiconductordevice, the semiconductor device may be another type of device than theSIP 16, such as a BGA or LGA (Land Grid Array), and the advantages ofthe present invention will be attained if it is manufactured byflip-chip bonding at least one semiconductor chip, which has been madethin by a grinding and flattening of its rear surface, to a wiringsubstrate with a non-conductive resin adhesive.

The present invention is suitably used for electronic devices andsemiconductor manufacturing technologies.

1. A semiconductor device comprising: a wiring substrate having a frontsurface and a rear surface; a first semiconductor chip which has a mainsurface and a back surface and is flip-chip bonded to the main surfaceof the wiring substrate through projecting electrodes; a secondsemiconductor chip having a main surface and a back surface and mountedover the first semiconductor chip by bonding its back surface to theback surface of the first semiconductor chip with an adhesive; anon-conductive resin adhesive interposed between the wiring substrateand the first semiconductor chip; and a sealing body formed over thefront surface of the wiring substrate, for resin sealing the first andsecond semiconductor chips, wherein the first semiconductor chip is madethin by grinding its back surface and the back surface is made flat bypolishing after grinding.
 2. The semiconductor device according to claim1, wherein the projecting electrodes are gold bumps and the gold bumpsare soldered to the flip-chip bonded portions.
 3. A method ofmanufacturing a semiconductor device, comprising the steps of: (a)grinding a rear surface of a semiconductor wafer to reduce itsthickness; (b) after the step (a), flattening the rear surface of thesemiconductor wafer; (c) after the step (b), dividing the semiconductorwafer into a plurality of semiconductor chips; (d) after the step (c),forming projecting electrodes over the plurality of semiconductor chips;(e) applying a non-conductive resin adhesive to the front surface of awiring substrate; (f) arranging the semiconductor chips over the frontsurface of the wiring substrate through the resin adhesive and pressinga back surfaces of the semiconductor chips to flip-chip bond thesemiconductor chips to the wiring substrate through the projectingelectrodes; and (g) sealing the semiconductor chips with a resin.
 4. Themethod of manufacturing a semiconductor device according to claim 3,wherein polishing is carried out in the step (b) to flatten the rearsurface of the semiconductor wafer.
 5. The method of manufacturing asemiconductor device according to claim 3, wherein wet etching iscarried out in the step (b) to flatten the rear surface of thesemiconductor wafer.
 6. The method of manufacturing a semiconductordevice according to claim 3, wherein the back surfaces of thesemiconductor chips are pressed by a block through a sheet member in thestep (f).
 7. The method of manufacturing a semiconductor deviceaccording to claim 6, wherein the sheet member is made of a fluororesin.8. The method of manufacturing a semiconductor device according to claim3, wherein a first semiconductor chip is flip-chip bonded to the frontsurface of the wiring substrate in the step (f), and a secondsemiconductor chip is mounted over the back surface of the firstsemiconductor chip through an adhesive, and the back surface of thefirst semiconductor chip and a back surface of the second semiconductorchip are bonded together by the adhesive after the step (f).
 9. Themethod of manufacturing a semiconductor device according to claim 3,wherein the non-conductive resin adhesive is a thermosetting resin. 10.The method of manufacturing a semiconductor device according to claim 8,wherein the adhesive for bonding the first semiconductor chip to thesecond semiconductor chip is a thermosetting resin.
 11. The method ofmanufacturing a semiconductor device according to claim 3, wherein thesealing resin used in the resin sealing of the step (g) is athermosetting resin.
 12. The method of manufacturing a semiconductordevice according to claim 3, wherein a plurality of solder balls areformed as external terminals over the rear surface of the wiringsubstrate after the step (g).
 13. The method of manufacturing asemiconductor device according to claim 3, wherein solder is pre-coatedover a plurality of electrodes to be flip-chip bonded over the frontsurface of the wiring substrate before the step (e).
 14. The method ofmanufacturing a semiconductor device according to claim 13, wherein thepre-coated solder is used to connect goldbumps as the projectingelectrodes for flip-chip bonding.
 15. The method of manufacturing asemiconductor device according to claim 3, wherein a pastenon-conductive resin adhesive is applied to the front surface of thewiring substrate in the step (e).
 16. A method of manufacturing asemiconductor device, comprising the steps of: (a) grinding the rearsurface of a semiconductor wafer to reduce its thickness; (b) after thestep (a), planishing the rear surface of the semiconductor wafer; (c)after the step (b), dividing the semiconductor wafer into a plurality ofsemiconductor chips; (d) after the step (c), forming projectingelectrodes over the plurality of semiconductor chips; (e) applying anon-conductive resin adhesive to the front surface of a wiringsubstrate; (f) arranging the semiconductor chips over the front surfaceof the wiring substrate through the resin adhesive; (g) after the step(f), pressing a planished back surfaces of the semiconductor chips toflip-chip bond the semiconductor chips to the wiring substrate throughthe projecting electrodes; and (h) sealing the semiconductor chips witha resin.
 17. The method of manufacturing a semiconductor deviceaccording to claim 16, wherein polishing is carried out to planish therear surface of the semiconductor wafer in the step (b).
 18. The methodof manufacturing a semiconductor device according to claim 16, wherein afirst semiconductor chip is flip-chip bonded to the front surface of thewiring substrate in the step (g), and after the step (g), a secondsemiconductor chip is mounted over the back surface of the firstsemiconductor chip through an adhesive, and the back surface of thefirst semiconductor chip and a back surface of the second semiconductorchip are bonded together through the adhesive.
 19. A method ofmanufacturing a semiconductor device, comprising the steps of: (a)preparing a plurality of semiconductor chips, each having a main surfaceand a back surface, the back surface being ground to be made thin, andbeing flattened by flattening after grinding; (b) forming projectingelectrodes over the electrodes of the plurality of semiconductor chips;(c) applying a non-conductive resin adhesive to the front surface of awiring substrate; (d) arranging the semiconductor chips over the frontsurface of the wiring substrate through the resin adhesive; (e) pressingthe flattened rear surfaces of the semiconductor chips to flip-chip bondthe semiconductor chips to the wiring substrate through the projectingelectrodes; and (f) sealing the semiconductor chips with a resin.